verilator: verilator (the fastest free Verilog HDL simulator)
verilator:
verilator: Verilator is invoked with parameters similar to GCC or Synopsys’s VCS.
verilator: It "Verilates" the specified synthesizable Verilog or SystemVerilog
verilator: code by reading it, performing lint checks, and optionally inserting
verilator: assertion checks and coverage-analysis points. It outputs single- or
verilator: multi-threaded .cpp and .h files, the "Verilated" code.
verilator:
verilator: homepage: https://www.veripool.org/wiki/verilator
verilator:
verilator: